There are many types of analog-to-digital converters (“ADCs”). Examples of ADCs include successive-approximation-register ADCs (“SAR ADCs”), pipelined ADCs, flash ADCs, and sigma-delta ADCs, among others. A conventional SAR ADC may include a sample and hold circuit (“S/H”) (also known as a track and hold circuit), a digital-to-analog converter (“DAC”), a comparator, a register, and SAR logic.
A conventional SAR ADC may include a switched capacitor DAC having an array of N capacitors of binarily weighted values. Unfortunately, such N capacitors conventionally may be associated with substantial calibration overhead and space consumption. Furthermore, clock buffers may have to be scaled accordingly to such N binarily weighted capacitors, which may add to the overall complexity and overhead as frequency is increased. For these reasons, conventional SAR ADCs may be frequency limited to lower operational frequencies than needed for many applications.
Accordingly, it would be desirable and useful to provide a SAR ADC that overcomes one or more of the above-described limitations of a conventional SAR ADC.